[Aaron Stillmaker]

Aaron Stillmaker

Ph.D. Candidate at the University of California, Davis
VLSI Computation Lab
Advisor: Dr. Bevan Baas
2211 Kemper Hall
ECE Department
University of California, Davis
Davis, CA 95616

astillmaker -a,t- ucdavis -period- edu

Brief Bio:
Aaron Stillmaker is a Ph.D. candidate in the VLSI Computation Lab in the Electrical and Computer Engineering Department at the University of California, Davis. Aaron was born and raised in Fresno, CA and recieved his BS degree in 2008 in Computer Engineering from the California State University, Fresno in the Smittcamp Family Honors College and his MS degree in 2013 in Electrical and Computer Engineering from the University of California, Davis. Aaron interned with the Circuit Research Lab under Intel Labs in Hillsboro, OR from September to December 2013. During his undergraduate work he held a long term internship at Pelco Inc.

University of California, Davis, CA
Ph.D., Electrical and Computer Engineering, 2008 – Present
Major: Digital Design and Computer Systems; Minor:Signals and Systems

University of California, Davis, CA
M.S., Electrical and Computer Engineering, 2013

California State University, Fresno, CA
B.S., Magna Cum Laude, Smittcamp Honors Scholar, 2008
Major: Computer Engineering; Minor:Bussiness


Research Interests:
Processor Architecture
DSP Applications
VLSI Design
Many-Core Processor Applications
Parallel Enterprise Workloads
Parallel Database Sorting Algorithms

Publications and Presentations:
Physical design of 4rd generation VCL many-core processor array "KiloCore2".

Test of 3rd generation VCL many-core processor array "KiloCore".

Physical design of 3rd generation VCL many-core 1,000 processor array "KiloCore".
Chip should be returning from packaging soon.

Designing parallel database sorting algorithms for the AsAP2 chip.
UCD Industrial Affiliates 2011

Characterizing the scaling of power and delay as technology sizes scale, so as to make better comparisons to circuitry in different techology sizes.
Technical Report

Researching enterprise workloads suitable for a fine-grained many-core processor array

Wrote a dual clock FIFO in Verilog for communication between two different clock frequencies.
Dual Clock FIFO


UC Davis:
TA: EEC 116 (VLSI Design), Fall 2012, for Dr. Bevan Baas

TA: EEC 70 (Computer Structure and Assembly Language), Winter 2011, 2012, and 2013, for Dr. Venkatesh Akella

TA: ENG 6 (Engineering Problem Solving), Spring 2011, for Dr. Bevan Baas

Fresno State:
TA/Lab Instructor: ECE 1L (Introduction to Electrical and Computer Engineering), Fall 2007 and Spring 2008, for Dr. Gregory Kriehn

Professional Services:

University of California, Davis
ECE Department: UC Davis
VCL Group: ECE Dept.: UC Davis
Dr. Bevan Baas

This page was last modified on December 8, 2014. Keywords:A. Stillmaker, Aaron Stillmaker