Bevan Baas

VLSI Computation Lab
Department of Electrical & Computer Engineering
University of California, Davis

2037 Kemper Hall
ECE Department
University of California
Davis, California   95616-5294   USA

530-752-0583 (ECE main office)
530-752-8428 (fax)

Quarter Course
  Fall 2017   EEC 116   VLSI Design Final Project winners and results
  Winter 2018   EEC 180B   Digital Systems II
  Winter 2018   EEC 281   VLSI Digital Signal Processing
  Spring 2018   EEC 180B   Digital Systems II

Office hours

Bevan Baas received a B.S. in electronic engineering from California Polytechnic State University in 1987, and M.S. and Ph.D. degrees in electrical engineering from Stanford University in 1990 and 1999 respectively.

From 1987–89, he served as a new product engineer working on the processor for a high-end minicomputer in Hewlett Packard's Computer Systems Division, Cupertino, CA. In early 1999, he joined Atheros Communications [wikipedia] as the second full-time employee after the founders and served as a core member of the team which developed the first IEEE 802.11a (54 Mbps, 5 GHz) Wi-Fi wireless LAN solution. The chipset began shipping in volume in September of 2001 and for one and a half years was the only shipping 802.11a chipset [ISSCC 2002]. Atheros became a publicly-held company in Feb. of 2004 and was purchased by Qualcomm in 2011. In 2003, Dr. Baas joined the Department of Electrical and Computer Engineering at the University of California, Davis as an Assistant Professor, where he currently supervises research for more than ten graduate students. He became an Associate Professor in 2008, and a full Professor in 2015.

Dr. Baas' research interests are in the algorithms, applications, architectures, arithmetic, circuits, VLSI design, and software tools for high-performance, energy-efficient, and area-efficient computation with consideration of the challenges and opportunities of future fabrication technologies. He is interested in both programmable and special-purpose processors with an emphasis on DSP, multimedia, and embedded workloads with recent projects targeting datacenter and scientific workloads. Projects include the AsAP (Asynchronous Array of simple Processors) programmable array processor chips (36 processors, 167 processors, 1000 processors), applications, and tools; Low Density Parity Check (LDPC) decoders; Fast Fourier Transform (FFT) processors; viterbi decoders; Advanced Encryption Standard (AES) ciphers; Synthetic Aperture Radar (SAR); H.264 video codecs; Display Stream Compression (DSC) codecs; sorting and string-search engines; and machine learning engines. His group is one of very few university groups in the world that design and fabricate programmable (and configurable special-purpose) processor chips. They have designed what are believed to be the #1 and #2 highest clock rate fabricated processors ever designed in a university, and among the largest deep-submicron CMOS chips ever designed in a university.

Dr. Baas was a National Science Foundation Fellow from 1990–93 and a NASA Graduate Student Researcher Fellow from 1993–96. He received the National Science Foundation CAREER award in 2006, Best Paper Award at the IEEE International Conference on Computer Design 2011, Best Student Paper Award third place at IEEE International Midwest Symposium on Circuits and Systems 2015, Best Student Paper Award third place at IEEE Asilomar 2014, "WACIest" Best-In-Session Paper at ACM/IEEE Design Automation Conference (DAC) 2010, and Best Paper nominations at IEEE Asilomar 2011 and IEEE BioCAS 2010. He supervised the research that earned the College of Engineering Zuhair A. Munir Award for Best Doctoral Dissertation Honorable Mention in 2013, and was awarded the Most Promising Engineer/Scientist Award by AISES in 2006.

He is currently an Associate Editor for the IEEE Transactions on VLSI Systems since 2016, and an Associate Editor for the IEEE Transactions on Circuits and Systems II since 2016. From 2007–12 he was an Associate Editor for the IEEE Journal of Solid-State Circuits and he has served as Guest Editor of IEEE Micro, March 2012; and IEEE Design & Test of Computers, January 2013. He has been a Visiting Professor at Intel's Circuit Research Lab in 2006, the University of Sydney in 2015–16, the National University of Singapore in 2016, and ST Microelectronics R&D in 2016.

He has served and is serving as: Track Program Co-Chair of the IEEE Conference on Dependable and Secure Computing 2017; Technical Program Committee member of the IEEE International Conference on ASIC (ASICON) 2017; Program Committee member of the IEEE/ACM International Workshop on Network on Chip Architectures (NoCArc) 2016, 2017; Technical Program Committee member of the IEEE/IFIP International Conference on Very Large Scale Integration (VLSI-SoC) 2014; Committee member of the International Solid-State Circuits Conference (ISSCC) Student Research Preview 2012, 2013, 2014; Program Committee Co-Chair of the IEEE HotChips Symposium on High-Performance Chips 2011; Parallel Architecture Co-Chair of the Design Automation Conference (DAC) 2011 Workshop on Parallel Algorithms, Programming, and Architectures; Program Committee member of the IEEE HotChips Symposium on High-Performance Chips 2009, 2010; Technical Program Committee member of the IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) 2010; Technical Program Committee member of the International Conference on Computer Design (ICCD) 2004, 2005, 2007, 2008, 2009; a member of the AISES Academic Advisory Council, and the original Technical Advisory Board of Soft Machines Inc. 2006–2016. He is a member of Tau Beta Pi, Phi Kappa Phi, Eta Kappa Nu, AISES, and a Senior Member of the IEEE.

My university web page. A short bio, and a slightly longer bio which are not kept up to date.

Research & Students

VLSI Computation Lab (VCL) home page

Research opening
I currently have an opening for a US Ph.D. student with an outstanding academic record. Due to funding limitations, I do not expect any openings for international Ph.D. students this coming year. Strong grades are a requirement. A completed MS, research experience, and publications are big pluses. Please contact me if you qualify and are interested.   A few student project examples.   A note to interested prospective students.

Undergraduate Research
I often have research projects available for UC Davis undergraduate students. I have found a strong GPA is the best predictor of research success so that is fairly important. Please contact me if you are interested.

Research Interests

Misc Items

Other Work

VLSI & Sig. Processing conferences, MIT Comp Arch list

Upcoming and Past Presentations

My personal web page

Last update: February 01, 2018
Keywords:B. Baas, B. M. Baas, Beven, Bevin, Bass