|All work must be done individually unless stated otherwise. All work should be submitted at one time. If the assignment is reviewed in class or solutions are made available, no credit is possible for late work. If the assignment was not reviewed in class, work may be submitted with a 1/3 reduction of remaining credit (i.e., 100% -> 67% -> 44% -> 30% ...) per day. Unreviewed late work may be submitted with a verifiable written excuse. Each homework sub-problem will be graded on a three-step scale: 0 (not a full effort), 1 (close but fundamental problem), and 2 (correct or with a very minor problem). For more challenging problems or those with many points, points may be multiplied, e.g., [0,2,4 pts] or [0,3,6 pts]; or graded on a similar five-step scale: 0% (not a full effort), 25% (between 0%-50%), 50% (close but fundamental problem), 75% (between 50%-100%), 100% (correct or with a very minor problem).|
|Notify the instructor of clear and significant grading errors within a week of being returned. Due to the inherent subjectiveness of grading and to be fair to all students, only truly significant mis-grades will result in a grade change. Submit to the instructor: 1) a short description of the suspected grading error, 2) the following statement on your regrade request with your signature immediately below it: "I certify that I have not altered this work in any way after it was returned to me. I understand that such altering would constitute a violation of the Code of Academic Conduct." To be fair to other students, detailed regrading requests will result in a re-examination of the entire work and may result in a decrease in the total score. Note that to discourage falsified regrading, some number of all graded assignments/labs/exams will be photocopied before being returned to students.|
|Date||Reading||Lecture||Notes & Slides||Assignments|
|Th, Sept 28||-||Course and VLSI introduction, VLSI fabrication technologies||
||Lab week 1: No lab|
|Tue, Oct 3||
||Abstraction of complexity, design styles||
• 2:Fab technologies, abstractions
• 3:Chip implement methods
• 4:VLSI is like art
|Read "Cramming more components onto integrated circuits," Gordon Moore, Electronics, April 19, 1965. This is the landmark paper which defined "Moore's Law."|
|Th, Oct 5||
Ch 2: CMOS Fab I
• 5:VLSI costs
• 6:Fab basics
|Lab week 2: Tutorials 1, 2, 3|
|Tue, October 10||-||
CMOS Fab II,
Full-custom layout, Stick diagrams
• 8:Fab examples
• 9:Layout & magic
Hwk 1, problems 1 and 4.
Due at the beginning of class.
For problem 4, use the
IEEE website to find the 2017 International Solid-State
Circuits Conference (ISSCC) proceedings.
Accessing the web site requires a subscription but is free
from campus. The ISSCC is widely considered the top chip
conference in the world for advanced chips.
|Th, October 12||
Ch 3: pp. 116-117 (latchup).
||Layout guidelines I||
• 11:Stick diagrams
• 12:Magic vs. GDSII/CIF
• 13:Layout Guidelines
|Lab week 3: Tutorials 4, 5, 6|
|Tue, October 17||
Ch 5.1-5.3.2, 5.4
Layout guidelines II,
nwell and pwell, Latchup,
Ch 5: CMOS inverter characteristics I: reliability
|Th, October 19||
Ch 3: pp. 104-113.
Sec 4.3.2: pp. 144-146 (resistance)
Ch 3: MOS resistance, capacitances
Hwk 2, Due at the beginning of class.
Lab week 4: Tutorials 8, 11
|Tue, October 24||
Ch 3: Sec. 3.5
Ch 3: Scaling
Ch 7: Sequential circuits, clocking
|• 14:Notes-ch3||Read "Design of Ion-Implanted MOSFET's with Very Small Physical Dimensions," Robert H. Dennard, et al., IEEE Journal of Solid-State Circuits, October 1974. This is the landmark paper which defined "Dennard Scaling."|
|Th, October 26||
Ch 7: pp. 326-334, 344-346,
||Ch 7: Sequential circuits II: ring oscs, latches and flip-flops||
• 15:Flip-flop schematics
Work through Irsim Tutorial.
Lab week 5: Simulating layout
|Tue, October 31||-||Sequential circuits III,||
Problems 1–4 due beginning of class. Problem 5 due by end of
lab Oct 27 or Oct 31.|
|Th, November 2||
Ch 6: pp. 236-251, 269-271
Ch 6: pp. 277-280
CMOS inverters: sizing for performance
||Lab week 6: Full adder design|
|Tue, November 7||
Chain of inverters design,
Ch 6: Combinational CMOS logic gates I
|• 16:Chain of inverters||
Problems 1–3 due beginning of class. Problem 4 due by end of
lab Nov 7; however Friday lab people may checkoff in
your section Nov 3.
|Th, November 9||Midterm
Covers all material discussed or assigned readings through Nov 2 and Hwk 4
Lab week 7: Flip-flops
|Fri, November 10||Veterans Day
Optional lab session at normal time 2:10–5pm
|Tue, November 14||
Ch 4 (all)
Combinational CMOS logic gates II,
ratioed logic, dynamic logic,
|Read "The Fanout-of-4 Inverter Delay Metric," David Harris, et al., unpublished, probably 1997. This paper introduces the concept of the "FO4" delay metric.|
|Th, November 16||-||
Pass transistor logic
Ch 4: Wires I
• 17:Pass gates (partial)
• 18:Wires I (partial)
|Lab week 8: More flip flops|
|Tue, November 21||
Ch 12: pp. 623-638, 657-669, 672-674
• 19a:Wires II (partial)
Due by end of lab Nov 21; however Friday lab people may checkoff
in your section Nov 16.
|Th–Fri, November 23–24||Happy Thanksgiving
Lab week 9: Final project
|Tue, November 28||
Ch 9: pp. 445-462 (pads, grids,...).
Chip-level structures and issues I
• 20:Wires III (partial)
|Th, November 30||
Sec. 9.3.2: pp. 462-464 (electromigration).
Chip-level structures and issues II,
• 25:Chip structures II (partial)
VLSI in the News: Move Over Graphene: IBM Expects Copper Interconnects to Hold the CMOS Line,
ExtremeTech, November 16, 2017.
Lab week 10: Final project
|Tue, December 5||
Ch 8: pp. 377-388, 396-406,
Ch H: pp. 721-737 (test).
Ch 12: Memories
• 22:Memories (partial)
Due by end of lab Dec 5 either checked off in person (preferred)
or by submitting paper copies of all work in lab or using the
|Th, December 7||
Std cell P&R chip design example
• 24:Pipelining and chip structures I (partial)
• 27:Std cell design
• 28:PackagingDEC 7
• 29:Packaging (partial)
• 30:Datasheet 132-pin PGA,
Next-Generation IBM System z Microprocessor,"
Warnock, et al., ISSCC, Feb 2015.
This paper describes a monster 5.2 GHz 678 mm2
17-metal-layer 22 nm IBM 2-chip system.
Reference: "Scaling Challenges of FinFET Architecture below 40nm Contacted Gate Pitch," Razavieh, et al., Device Research Conference, June 2017. Detailed recent paper giving an overview of FinFET transistors with gate lengths as small as 7 nm. (note 7 nm has contacted gate pitch of 48 nm which is 13.7 λ)
Reference: "Is Dark Silicon Useful?," Taylor, et al., Design Automation Conference (DAC), June 2012. This is the landmark paper which describes "Dark Silicon."
|Mon, December 11
1:00 pm: Electronic files uploaded to canvas
1:00 pm–5:00 pm (sign up on doodle poll): paper submission and functional demonstration to TA in lab
|Tue, December 12, 8:00-10:00am||Final exam