EEC 116 - Special Nanometer-Scale Rules
1. Polysilicon width (MOSFET channel length)
Polysilicon width may be only 2 λ unless stated otherwise,
or as necessary with polysilicon contacts and vias.
2. Polysilicon 100 λ length limit
Polysilicon wires may not be longer than 100 λ beyond the
point where a metal wire (coming from the driver) transitions to a
The rule must be satisfied for the path from the source driver to
every destination in the metal/poly network.
(metal) (poly) (metal)
3. nwells and pwells
Draw nwells around all PMOS transistors and pwells around all NMOS
transistors and connect them to Gnd or Vdd as appropriate.
Place at least one nwell/psubstrate contact for every 3 squares of
4. Polysilicon, Deep Sub-micron
- Polysilicon may be oriented in only one direction
for the entire chip.
- Polysilicon spacing may be only
a) 8 λ, or
b) greater than 16 λ
unless stated otherwise.
- All polysilicon that is used for a functional circuit must have other
polysilicon at a distance of 8 λ the entire length of both
of its long edges. This implies the need for "dummy" poly in some cases.
See Fig. 1.
- Rule #4.4 may be violated for a maximum length of 3 λ
as shown in three examples in Fig. 1.
- Rule #4.4 may be violated for polysilicon-to-metal contacts
but the poly contact may extend beyond the poly "wire" by a maximum
of 2 λ as shown in Fig. 1.
Figure 1. Example polysilicon structures which satisfy traditional MOSIS
rules (top row), and functionally identical ones which satisfy the new
"nanometer scale" rules (bottom row).
- clarify: stacked vias with poly
- possibly add wide metal rules
2010/11/23 Added nwell/pwell rules
2010/11/24, 0400 Corrected rule 3.4 to 16 lambda, not 12 lambda
2013/10/14 Added detail to ascii figure for polysilicon rule
2013/11/21 Added examples of exceptions to rule #2 in Figure 1,
and minor tweaks to polysilicon ascii figure
2014/10/23 Moved poly width to rule #2, plus other reorganization