For layout, add wells, and well/substrate connections as described in lecture; and follow Rules 1, 2 & 3 on the "Special Nanometer-scale rules for EEC 116" web page.

- [100 pts] Draw a gate-level circuit schematic (5 pts), a transistor-level
circuit schematic (10 pts), and a stick diagram (10 pts) for an
efficient Full Adder gate using only inverter and NAND gates,
and using metal1, metal2, and metal3 (metal3 sparingly only when helpful)
for routing.
Layout the cell

*fulladder*in magic and label inputs a, b, cin and outputs sum_ (inverted version of the true sum) and cout and place them so the tiles can be abutted with correct operation (50 pts). Do not inefficiently generate the true sum and then invert it; rather, generate the efficient direct equations for sum_.Make all NMOS transistors 4 lambda wide and all PMOS 6 lambda wide, and all transistors with minimum length channels.

- [50 pts] Simulate the fulladder cell in irsim in one simulation
with all possible input combinations and clearly show the inputs and
correct outputs in an irsim output listing or waveform (40 pts). State
how many combinations are correct (10 pts).
- [35 pts] Using the magic "getcell" command, place 8 copies of the
full adder cell into a new cell called
*add8*, and add a single inverter with folded transistors (PMOS 20 lambda wide, NMOS 10 lambda wide) to each of the eight sum_ signals. Paint small extensions onto each input, output, Vdd, and Gnd node, and place new labels with the names a0-a7, b0-b7, sum0-sum7, cin0, cout7. - [75 pts] Simulate the add8 cell in irsim in one simulation with
the following input combinations and clearly show the inputs and
correct outputs sum and cout7 in an irsim output listing or waveform
(65 pts). State how many tests are correct (10 pts).
a = 00000000, b = 00000000, cin0 = 0 a = 00000000, b = 00000000, cin0 = 1 a = 00000001, b = 00000001, cin0 = 1 a = 00000101, b = 00001011, cin0 = 0 a = 00000001, b = 00111111, cin0 = 0 a = 11111111, b = 00000001, cin0 = 0 a = 11111111, b = 00000000, cin0 = 1 a = 00000001, b = 11111111, cin0 = 0 a = 00000000, b = 11111111, cin0 = 1

- [2 x 10 pts] Eight inverters are connected in a chain with the
first one having NMOS W = 4 lambda and PMOS W = 8 lambda. If the fanout
of every gate is two, what are the widths of the transistors in the
eighth inverter? What if the fanout is ten?
- [4 x 10 pts] Find the Ron for the following 0.25 um, L = 2 lambda
transistor circuits.

a. NMOS W = 4 lambda, Vdd = 2.5 V

b. Two NMOS W = 8 lambda, Vdd = 1.5 V devices in parallel

c. An NMOS W = 4 lambda in series with an NMOS W = 20 lambda, Vdd = 2 V

d. PMOS W = 15 lambda, Vdd = 1.75 V (estimate it using a reasonable method)

Updates:

2014/10/23 Posted