EEC 116 - Homework 4

Do your work individually. For this assignment, use standard magic design rules plus the EEC 116 Nanometer-scale rules.

210 pts total.

  1. [60 pts] Flip-flop cell. Use the positive-edge triggered, master-slave flip-flop called the "Safest Flip-Flop" in the handout posted on the course web page. Include two inverters inside each flip-flop to buffer the single clock input and generate clock_buf and clock_buf_bar (for internal cell use only). The clock input must drive only one inverter and no other circuits.


  2. [25 pts] Design a large buffer cell consisting of a single inverter which abuts directly to the "Q_bar" output of your flip-flop. The inverter must have a PMOS width of 85 λ and an NMOS width of 50 λ and must use folded transistors. Show the layout to one of the TAs during the lab session in which it is due, for the buffer abutted to your flip-flop cell.

  3. [25 pts] A cell in magic called tenFFs which is composed of 10 instances of the flipflop cell. Design it with inputs Vdd, Gnd, clock, in00 - in09, and outputs out00 - out09.

  4. [100 pts] Simulation. Layout a cell called top which instantiates one copy of tenFFs and connects all FFs into one long chain by connecting the output of FF00 to the input of FF01 and so forth. No credit can be given unless the layout is complete and fully functional.

    Test top in irsim with the following pattern:

    1) Fill the FF chain with all "0"s
    2) Inject a single "1" into the chain
    3) Fill the FF chain with all "0"s (produces a "walking 1" pattern)
    4) Fill the FF chain with all "1"s
    5) Inject a single "0" into the chain
    6) Fill the FF chain with all "1"s (produces a "walking 0" pattern)
    
    Demonstrate the irsim waveform to your TA during lab.



Updates:
2014/11/10         Posted