EEC 116 - Homework 4

Do work individually.

  1. [3 x 10 pts] Find the Req for the following 0.25 μm transistors.
    a. PMOS W = 6 lambda, L = 2 lambda, Vdd = 2.5 V
    b. Two NMOS W = 5 lambda, L = 2 lambda, Vdd = 1.5 V devices in parallel
    c. PMOS W = 14 lambda, L = 2 lambda, Vdd = 1.75 V (estimate it using a reasonable method)
    d. PMOS W = 2 lambda, L = 8 lambda, Vdd = 2.5 V

  2. [20 pts] All transistors in a 0.25um CMOS 3-input NAND gate are 10 lambda wide and 2 lambda long. Calculate the input capacitance of all inputs if Cox = 6 fF/um^2

  3. [45 pts] The following gates contain PMOS transistors that are 2 times as wide as their NMOS transistors. NMOS transistors have source/drain dimensions of LS = LD = 1 μm and W = 3 μm, where LS and LD are the full source/drain length. For each, [5 pts] draw a schematic and [10 pts] write an expression for the total junction capacitance on each gate's output in terms of Cj and Cjsw
    a. Inverter
    b. 3-input NOR gate
    c. 2-input NAND gate

  4. [45 pts] The heart of the original Apple iPad is the Apple A4 chip which operates at 1.0 GHz and is believed to utilize ARM Cortex-A8 CPUs. The chip is believed to have been built with Samsung 45nm technology. Let's assume it dissipates 5 watts using a 1.0 V power supply.
    a. [10 pts] If a prototype made in 65 nm is available, what speed and power consumption will the chip likely have assuming constant-field scaling?
    b. [15 pts] If the supply voltage on the 65 nm part were scaled to 0.7 V, what will the power consumption and speed be then?
        Make the (overly simple) assumption that the clock frequency drops linearly from the maximum frequency at the maximum voltage, to zero Hz at Vdd / 2.
    c. [10+10 pts] i) What supply voltage should be used by the 45 nm part to set the power consumption of 2.5 Watts? ii) At what speed would the processor then operate?

  5. [30 pts] Draw a simplified circuit diagram of a clock network which clocks 5 functional units in a processor: adder, subtractor, multiplier, divider, square root. Each functional unit contains 32 flip-flops and must be designed so that its clock can be shut off to save power. The maximum fanout anywhere in the system is 4. The diagram should not show all parts of the clock system, but must include enough detail so that the structure and topology is clear.

  6. [80 pts] An analog circuit requires a resistor of 35,000 Ω. Design 4 separate resistors made of the materials: nwell, ndiff, poly, and metal1 in four different standard cells which must be 40 lambda high and with a minimum width. Consider the resistance of all corners to be zero.
    a. [4 x 10 pts] Calculate minimum cell width showing all calculations
    b. [4 x 10 pts] Layout in magic without DRC violations

  7. [150 pts] Design the circuit and layout for a cell called zerodetect which detects when a 49-bit bus is equal to zero. The input is routed in 49 parallel metal3 wires with minimum width and minimum spacing. Use only inverter, NAND, and NOR gates as necessary. The maximum fanout fanin for every gate is three gate inputs.

    In the top-level cell top, place a copy of the zerodetect subcell, route small metal3 stubs for the 49 inputs and single output zero49 next to the subcell. Short every 8 inputs together in top, and put the following labels on each group of eight seven inputs: in0, in1,..., in7 in6. Simulate the circuit by toggling various values on the inputs and showing that the output is correct for at least 50 key test cases.

    Submit the following:

    1. [5 pts] circuit schematic of zerodetect cell
    2. [5 pts] sketch of floorplan of zerodetect cell
    3. [5 pts] area of zerodetect cell in lambda^2
    4. [5 pts] area of zerodetect cell in micron^2
    5. [130 pts] irsim waveform demonstrating correct operation

    Parts 3-5 can be given points only if the circuit is fully functional.

2013/10/25         Posted
2013/10/28, 15:00  Corrections to problem 7
2013/10/28, 19:00  Clarifications to problem 4