- [20 pts] A high-performance microprocessor was fabricated in a
0.25 um technology and operates at 100 MHz, consuming 10 Watts using
a 2.5 V power supply. State any necessary assumptions.
a. [5 pts] Using constant-field scaling, what speed and power consumption will the same processor
have if it is scaled to a 65 nm technology?
b. [5 pts] If the supply voltage on the 65 nm part were scaled to 0.7 V, what will the power
consumption and speed be then?
c. [5+5 pts] What supply voltage should be used to fix the power consumption at 1.0 Watts? At what
speed would the processor then operate?
- [20 pts] All transistors in a 0.25um CMOS 3-input NAND gate are 10
lambda wide and 2 lambda long. Calculate the input capacitance of all
inputs if Cox = 6 fF/um^2
- [4 x 10 pts] Find the Req for the following 0.25 um transistors.
a. NMOS W = 4 λ, L = 2 λ, Vdd = 2.5 V
b. PMOS W = 8 λ, L = 2 λ, Vdd = 2.5 V
c. NMOS W = 15 λ, L = 2 λ, Vdd = 1.0 V
d. Two NMOS W = 5 λ, L = 2 λ, Vdd = 1.5 V devices in parallel
- [15+15 pts] A certain material has R_square = 0.08 Ohms when it
is 0.01 mm thick. The material is formed into the shape shown below
and is 0.025 mm thick. Since techniques to calculate the resistance
of a corner are complex, approximate the resistance by calculating a
reasonable lower bound and upper bound resistance between points A and B.
Explain your reasoning.
12 mm A -+ |
| | 40 mm
- [20 pts]
An isolated metal3 wire is 1.5 mm long, 1 um wide, and runs over
a large sheet of metal1. It is driven by a CMOS driver with very
fast output rise and fall times. How will the delay change for the
You may give your answer in a general sense that is true for all
technologies, or use 0.25 um data from book pp. 143-145 or inside
Explain your reasoning for each.
a) [4 pts] If the wire length is doubled.
b) [4 pts] If the wire length is cut to 1/3.
c) [4 pts] If the wire width is doubled.
d) [4 pts] If the wire is run over open silicon substrate instead
e) [4 pts] If a large 10 um wide metal4 wire is run over the wire.
- [40 pts]
The figure below shows a signal distribution network built in 0.25 μm
CMOS whose features are described in Table 4.2 on page 143. All wires
are 0.75 μm wide and are routed in metal1. There are loads at each of
the lettered nodes in the network that are well-modeled by capacitances
of the following values: A,B,C = 100 fF;
D,E = 150 fF.
For wire resistance, assume wires are made of Aluminium
and choose and state your assumptions.
1mm 2mm 1mm
source ------+-----------+----- D
1mm | | 1mm
+---- A E
a) [10 pts] Draw the equivalent circuit and annotate the values of resistors
and capacitors, using lumped R and C models for the network.
b) [30 pts] Since the maximum delay in a digital system is the one that limits
the clock frequency, find the maximum dominant time-constant
(considering all nodes)
in the network.
- [30 pts] Draw a simplified circuit diagram of a clock network which
clocks 5 functional units in a processor: adder, subtractor, multiplier,
divider, square root. Each functional unit contains 32 flip-flops and
must be designed so that its clock can be shut off to save power. The
maximum fanout anywhere in the system is 4. The diagram should not show
all parts of the clock system, but must include enough detail so that the
structure and topology is clear.
- [80 pts] An analog circuit requires a resistor of 35,000 Ω.
Design 4 separate resistors made of the materials:
nwell, ndiff, poly, and metal1 in four different standard cells which
must be 40 lambda high and with a minimum width.
Consider the resistance of all corners to be zero.
a. [4 x 10 pts] Calculate minimum cell width showing all calculations
b. [4 x 10 pts] Layout in magic without DRC violations