EEC 116 - Final Project

This project consists of the design and layout of a chip which finds the maximum value among the last four 12-bit numbers to enter the chip. It is a type of sliding window filter often used in digital signal processing workloads.

All work must be done individually.


Figure 1. Top-level block diagram

Core (core.mag)

Chip (chip.mag)

Top-level test environment (top.mag)

Other requirements

Functional testing

Measuring the maximum clock rate (minimum clock period or longest logic path delay)

Points

Total: 420 points = 270 pts + 150 maximum performance pts

Submitting your work and meeting with your TA

  1. Canvas submission: All *.mag files and NO *.ext, *.sim, or *.cmd files (except mysetup.cmd with your shortest achievable stepsize), must be uploaded in a single .zip file by the posted deadline.

    If you care about your grade, perform a "practice run" on your .zip file in an empty directory after creating it, using fresh copies of tbtest.cmd and 1clk.cmd, to make sure your layout is complete and all simulations work at your minimum stepsize during your checkoff meeting.

  2. Paper submission: Fill out and submit 1) this Key Results Summary Sheet, and 2) other requested printed material, to your TA during your checkoff meeting.

  3. Shortly after the posted deadline, all .zip files will be downloaded from canvas (late submissions will not be tested).

  4. Checkoff meeting: Meet with your TA at your reserved time. The following steps will be followed for each student during the checkoff.

    1. mkdir student_name

    2. mv download.zip student_name/

    3. cd student_name/

    4. unzip download.zip

    5. rm *.ext *.sim tbtest.cmd 1clk.cmd

    6. less mysetup.cmd   (give it a quick look)

    7. cp ../tbtest.cmd ../1clk.cmd ./

    8. magic116 top.mag   (layout examined, extracted)

    9. ext2sim116 top

    10. irsim116 top.sim
      @ tbtest.cmd

    Be logged into a workstation in case there are any very simple issues that might come up however there is no time for debugging.

Miscellaneous



EEC 116 | B. Baas | ECE Dept. | UC Davis
2023/12/02  Posted
2023/12/04  Corrected the process of converting unsigned to 2's complement--it 
            is done by appending a zero bit.
            Removed negative inputs from Functional Testing section.