4-8pm Lab A01
4-8pm Lab A04
9am-1pm Lab A03
9am-1pm Lab A02
Prelabs. Except for Lab 1, prelabs are due at the beginning of the indicated lab section. They will be graded quickly on a scale from 0-5 points by your TA. The on-time deadline is 15 minutes after start of class. Unfortunately, points can not be given for the prelab portion after this time.
Lab circuit checkoffs are due at the beginning of the lab section
the following week immediately after prelab checkoffs (see Assignments
They are graded on the following scale (note there is no 4):
0 Little attempt made
1 Not fully built
2 All there, but not working
3 Just about correct
5 Totally correct
Lab reports are due at the same time as the lab circuit checkoffs. Due to the large amount of grading for TAs, and because of the fast pace of material in lab, credit for late lab reports is not possible.
A lab report cover sheet must begin every lab report. Written work may be done on any type of paper (though graph paper will generally produce a better result) and must be neat whether typed or hand-written. Bound lab books should not be used.
Meets in 2110, Kemper Hall
Open times: Mon-Th 8am-10pm, Fri 8am-7pm, except when in use by other courses. It is normally closed on Saturdays and Sundays. The TA will normally close up the lab and ask students to leave at the end of the 4-hour lab period (esp. the night labs).
If you wish to work in the lab on Saturdays, it may possible to open it. If you will definitely be there on a particular Saturday and need TA help, notify your TA and if there is sufficient interest, a TA will be there for part of the day.
Each lab period contains three main sub-periods:
Submit your Prelab to your TA as soon as you arrive and they will be checked-off and returned in the first ~10 minutes of the period.
You may go to another section and use the equipment only if there is space available. The students for that section have priority for the equipment and assistance from the TA. This is the priority for workstations in 2110 during lab times:
For several logistical reasons, only your section's TA can sign off your lab. I realize that is not the most convenient option for students, but it is necessary so TAs can focus on the students in their own section during labs. The only exception is that the TA present during a Saturday session may sign off only the circuit portions of labs for students from other sections.
Logging into computers in room 2110 requires that you have a standard ECE account name and password, which you should have if you are enrolled in the course. If you are having problems with your account, contact ECE IT support. To make sure the first lab goes smoothly, try to log in to a lab machine during open lab hours before your first lab. Files you save on your computer in 2110 are saved onto only the computer on which you work. So you will not see those files if you later work on a different computer. A nice solution is to make a copy of your files on a USB drive.
The Quartus simulation tool requires knowledge of the location of the license server. Due to a Windows complication, this may cause the program to give the message, "License file is not specified." If this happens, select either option: 1) Use the LM_LICENSE. This option should set automatically the firstname.lastname@example.org license and click OK. 2) If you have a valid license file, specify the location of your license file. Then type: email@example.com and click OK.
A summary of equipment needed for 180A. You must bring your own protoboards (a.k.a., solderless breadboards) and wire cutters to lab when needed.
Lab grades will be adjusted so the average grade for each lab section
will be the same.
Normally TAs will not be able to debug students' circuits in detail
so they are available for other students. If your TA agrees to assist you in
debugging your circuit, show your TA your design materials and documentation
(e.g., Lab circuit schematics - 3 types, K-maps, timing
diagram, etc.) first. If your circuit wiring is difficult to follow,
your TA may ask you to re-wire neatly first. Normally, TAs will focus
on teaching debugging techniques rather than finding a particular bug in
Normally TAs will not be able to debug students' circuits in detail so they are available for other students. If your TA agrees to assist you in debugging your circuit, show your TA your design materials and documentation (e.g., Lab circuit schematics - 3 types, K-maps, timing diagram, etc.) first. If your circuit wiring is difficult to follow, your TA may ask you to re-wire neatly first. Normally, TAs will focus on teaching debugging techniques rather than finding a particular bug in your design.
No food or drinks are allowed in the lab. Equipment is connected to an alarm system so be careful to not move equipment which could set off the alarm.
Homeworks will normally be due Friday at 4:00pm in Room 2131 and will be returned in your lab section after grading. Unfortunately, late homeworks cannot be accepted except for verifiable medical excuses approved by the instructor.
Each major portion of each problem will be graded on a three-point scale: 0 (not a full effort), 1 (close but fundamental problem), and 2 (correct or with a very minor problem). For more challenging problems, points may be multiplied; e.g., [0,2,4 pts] or [0,3,6 pts].
The final exam is cumulative but with an emphasis on material since the midterm.
|Date||Reading||Lecture||Notes and Handouts|
|Tue, Jan. 6||Unit 1||Course introduction, binary arithmetic, 2's complement review||
|Th, Jan. 8||Unit 2||Boolean algebra: basic operators and theorems||Unit 2a
|Tue, Jan. 13||Unit 3
|Boolean theorems cont'd; SOP, POS||Unit 3|
|Th, Jan. 15||Unit 5||Minterms, maxterms, incompletely specified functions||
|Tue, Jan. 20||
|Th, Jan. 22||Karnaugh Maps II, Implicants||Unit 5 Extra|
|Tue, Jan. 27||
Unit 9 (muxes only)
|Th, Jan. 29||Unit 7||
Multi-level circuits, NAND, NOR
Unit 9, muxes II
|Tue, Feb. 3||
|Timing and hazards
|Th, Feb. 5||
|Decoders, encoders, ROMs,||
|Tue, Feb. 10||Unit 11||ROMs II, PLDs, PLAs, wired AND/OR,||
Handout: PLA example
|Th, Feb. 12||Midterm
Last Name A-L: 115 Hutchison
Last Name M-Z: 55 Roessler
|Tue, Feb. 17||Unit 4.7
Clockless latches, Level-sensitive latches, Flip-flops,
Handout: Flip-flop reset and preset
|Th, Feb. 19||Unit 13||
Registers, Shift registers, Binary counters, General counters
|Tue, Feb. 24
Finite State Machine analysis: Moore
Finite State Machine analysis: Mealy
|Th, Feb. 26||Finite State Machine design, state assignments|
|Tue, Mar. 3||Unit 15||Quiz 3
Moore binary vs. Mealy binary vs. Moore One-hot design example
|Th, Mar. 5||Unit 16||
State assignment guidelines,
Lecture 18 notes
|Tue, Mar. 10||Unit 18||Sequence detection||
Lecture 19 notes
|Th, Mar. 12||
Critical timing relationships,
fast adders, multipliers, shifters
|Th, Mar. 19
|Week||Prelab due and
work in Lab
|Lab report due at
beginning of lab section
|Homework problems |
(Problems in italics have their solution in the textbook;
Problems in gray are tentative until approximately the Thurs 8 days
before the due date, depending on material covered in lecture)
|Jan 6 - Jan 9||-||-||-||-
|Jan 12 - Jan 16||Lab 1||-||1||
Unit 1: Unit 1: 1, 3, 4, 5 (do subt. by adding 2's comp),
7, 8, 35
Unit 2: 1, 2, 4, 11ace, 13ac, 15b, 16a, 23bd, 25c, 26a
|Jan 19 - Jan 23||Lab 2
Lab Instrument Tutorial
Unit 2: 27, 29b
Unit 3: 1, 2, 3, 4, 5 (do not submit these five)
9, 11, 15de, 16a, 17ad, 25ab,
Unit 4: 1a & b, 2b
|Jan 26 - Jan 30||Lab 3||Lab 2||3||
Unit 4: 3, 5, 16, 19, 24, 27, 35a
Unit 5: Study guide 1-8, 1, 2 (do not submit these ten)
4, 8, 14abc, 19, 22fg, 28
|Feb 3 - Feb 6||Lab 4||Lab 3||4||
Unit 5: 26a, 32, 33
Unit 6: 1 (do not submit this one)
2, 3, 16
Unit 9: 1, 15, 19
|Feb 10 - Feb 13||no new lab||-||5||
Unit 7: 1, 4, 21df
Unit 7: 5, 27, 32, 39
Unit 8: 1, 2, 9, 10
Unit 9: 4a, 14, 20, 25, 27, 29ab ("invalid" means "unrepresentable")
|Feb 17 - Feb 20||Lab 5||Lab 4||6||
Unit 9: 8a, 29c (PLA)
Unit 11: 1, 2, 7, 11, 14, 19, 21
29 (do not submit this one)
|Feb 24 - Feb 27||Lab 6||Lab 5||7||
Unit 12: 3, 6, 7b, 8b, 30, 32
Unit 13: 1 (do not submit this one)
Unit 13: 2, 3
|Mar 3 - Mar 6||Lab 7||Lab 6||8||
Unit 13: 13, 17, 20, 24
Unit 14: 1, 2, 3 (submit all three)
|Mar 10 - Mar 13||Lab 7 con't||Lab 7
Extra sessions Sat, Mar 14:
Checkoffs Mon, Mar. 16:
Tue, Mar. 17 3pm in hwk box
Due Tue, Mar. 17 3pm
in hwk box
Unit 14: 6, 8, 10, 13, 26
Unit 15: 3, 4, 9, 11, 20
Unit 16: 8, 20
Suggestion: the fastest way to get a design working is to spend time debugging and testing with pencil and paper. Draw waveforms, think of test cases, and think through various modes with paper and pencil. Make sure you know exactly how each part works and be fairly confident of what is right even before you enter the design into the computer, much less start wiring up your board. I guarantee your understanding will be far greater, you will have a much greater chance of it working, and assuming it works, you will be done much sooner if you do this.
Suggestion: carefully check your pin assignments and/or signal polarities (active high or low) before wiring up your board.
Students may attend other sections in the 10th week and try to get their labs checked off but will have the lowest priority in terms of benches and TA time (it is likely none will be available). Since checkoffs are due during the assigned lab period, late checkoffs will receive substantial point reductions—likely 1/2 earned points. This is required to avoid overloading later lab sessions.