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EEC 180B - Digital Systems II
Spring 2018

General Course Information

Graded Work and Policies

Lab Information

Course Topics, Slides, Notes, and Handouts

Future details are tentative.

Date Reading Lecture Notes, Handouts, and Reading
Tue, April 3 Chapter 1, 2
Chapter 3 if needed
Course introduction
Digital design overview
(Basic units)
1:Lecture 01
Th, April 5 Chapter 6 if needed
Chapter 7 (Verilog)
Appendix A
Basics of digital systems
Design flow HDL to HW
Verilog introduction
2:HDL to HW
3:Verilog I: OverviewAPR 10
Tue, April 10   Verilog language basics
Verilog operators
4:Verilog IIa: BasicsAPR 12 minor, APRIL 25
5:Verilog quick ref guide, S. Sutherland (skim quickly)
Th, April 12 Chapter 8 (Comb. Blocks) Verilog Combinational logic
Verilog wire, assign
Verilog reg, always block
6:Verilog IIb: Basic Combinational logicAPR 25
 
Tue, April 17 Chapter 9 (Comb. Examples) Time and Verilog delays
Verilog common mistakes I
7:Verilog III: Time and delay
8:Verilog IV: Common mistakesAPR 18, APR 25 very minor
9:Example: NAND2
Th, April 19   Verilog common mistakes II
Verilog Testing I: commands, approaches
10:Verilog VI: TestingAPR 18; MAY 8 #93 plus minor; MAY 9 minor
Tue, April 24   Quiz 1
Verilog Testing II: verifying correctness, tools, test data sources, directory layout
 
Th, April 26 Chapter 10 (Binary #s, Arith)
Chapter 11 (Fixed/Float Pt)
Decoder design
Decoders with predecoding
Binary number formats
Binary coded decimal (BCD)
Binary add/sub I
11:Decoders
12:Binary formats, add/subMAY 7 #71-73
Tue, May 1 Chapter 13 (Arith. examples)
Binary add/sub II
Sign extension for 2's complement
Binary multiplication
13:Sign extension
14:Multipliers
Th, May 3

Chapter 14 (Seq. Logic)
Encoders
Flip-flops
Flip-flops with reset, preset, enable
Control circuits
Counters
15:FFs and registersMAY 3
16:Control I
Tue, May 8   Midterm
Wellman 2
Th, May 10 Chapter 16 (Datapath Seq. Logic)
Review: four verilog constructs
State machine design
State machine implementation
17:Four verilog constructs
18:Control II
Tue, May 15 Chapter 17 (Factoring FSMs)
Chapter 19 (Seq. Examples)
FSM example
Interfacing with unsync inputs: debouncing
Interfacing with unsync inputs: edge detection
19:Example FSM block diagram
20:Interfacing input signals
Th, May 17 Chapter 25 (Memory Sys)
 
Overview: Memories
Overview: ROMs
Memories in verilog
Pipelines I
Pipelined block diagrams
21:Overview:MemoriesMAY 19 #257, MAY 21 #257-259, MAY 22 #199
Tue, May 22 Chapter 23 (Pipelines)
 
Pipelines II
22:Counter example with four views (view in slide show mode)
Th, May 24 Chapter 15 (Timing)
 
Quiz 2
Clocks
Multi-rate/Variable clocks
23:ClocksJUN 5 #269
24:Variable-freq clocks
25:Basic diagramsMAY 30, JUN 5
26:Steps to design systems
Tue, May 29   Multi-rate/Variable clock verilog examples
ROMs: combinational synthesized
ROMs: macros, block memories
Building larger memory systems
M9K memory blocks
27:M9K memoriesJUN 5 #117,118
 
Th, May 31 Chapter 21 (Sys-Level Design)
 
Data word growth and reduction
Datapath design
Arithmetic: Rounding
28:Rounding
 
Tue, June 5 Chapter 22 (Interface & Sys-Level Timing)
Chapter 24 (Interconnect)
Datapath design example
Arithmetic: Saturation
Critical timing requirements of digital systems
29:Saturation
Th, June 7 Chapter 20 (Verif. and Test)
Timing example
Memories
Generating complex functions
Block interfaces, timing, interconnect
System-Level design
Semiconductor fabrication technologies
Field-Programmable Gate Arrays (FPGAs)
Static Timing Analysis
Arithmetic: MAC, ALUs; Verification and test
30:Memories II
31:Generating complex functions
32:Fabrication technologies
33:Estimating chip area
34:FPGA tutorial, 7 pages
35:FPGA vendors and major internal components
36:Static timing analysis
37:Nangate std cell library datasheet, Typical corner (canvas)
38:Nangate std cell library verilog definitions (canvas)
Wed, June 13
6:00–8:00pm
  Final Exam
Last Names A–G   Wellman 212
Last Names H–O   Olson 106
Last Names P–Z   Olson 206

Assignments

Future details are tentative.

Week Prelab due and
work in Lab
Lab report due at
beginning of lab section
Hwk due
Friday 5:00 pm
in hwk box
Homework problems
(Problems in gray are tentative until approximately the Thurs 8 days
before the due date, depending on material covered in lecture)
April 2 – April 6 - - - -

April 9 – April 13 Lab 1APR 4     

- - -

April 16 – April 20

Lab 2
Lab2.part2_testbench.v
Lab2.part3_template.v
Lab 1 -

April 23 – April 27

Lab 3APR 23
testgen.v
testgen_tb.vt (reference testbench for testgen.v)
Lab 2 -
April 30 – May 4

Lab 4MAY 1
Lab 3 1
8.11, 8.20
10.1, 10.5, 10.14, 10.16, 10.23, 10.26, 10.40
11.3, 11.4, 11.11, 11.13, 11.14
May 7 – May 11
Lab 5MAY 6 minor
Cover sheet
Lab 4 -
-

May 14 – May 18 Lab 6
Cover sheet
Lab 5
2
13.14
14.6-14.8, 14.18-14.19
16.4-16.5, 16.6
May 21 – May 25 Lab 7MAY 25
Cover sheet
Lab 6
-
-

May 28 – June 1 Lab 8JUN 5, JUN 7
jpeg2v_v6a.m (v. 1.0)
Cover sheet
Lab 7
3
25.1, 25.2 using Handout 21 primitive instead
23.1, 23.5, 23.9
June 4 – June 8 - -
4
15.1, 15.4, 15.8, 15.10, 15.19
    "contamination dly" = min dly from input to output
21.1
22.1–3 (only two examples each)
Additional lab hours:
  •   Saturday, June 2, 2–4pm
  •   Saturday, June 9, 2–5pm
  •   Tuesday, June 12, 4–6pm, Baas pre-final office hours, Kemper 2037
  •   Wednesday, June 13, 9:30–10:30am, Cui pre-final office hours, Kemper 2110
You must come to your correct section for checkoffs
Monday, June 11
    9am–12pm A04, Satyabrata
    12pm–3pm A01, Peiyao
    3pm–6pm A02, Tim
Tuesday, June 12
    10am–1pm A05, Shifu (note not in normal order)
    1pm–4pm A06, Jin
Lab 8
-
 


Videos of previous labs



Changes made will generally be colored green, except basic information in tables.

Last update: June 13, 2018