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EEC 180B - Digital Systems II
Winter 2018

General Course Information

Lab Information

Course Policies

Course Topics, Slides, Notes, and Handouts

Future details are tentative.

Date Reading Lecture Notes, Handouts, and Reading
Tue, Jan 9 Chapter 1, 2
Chapter 3 if needed
Course introduction
Semiconductor fabrication technologies
1:Lecture 01
2:Fabrication technologies
Th, Jan 11 Skim Chapter 5
Chapter 7 (Verilog)
Appendix A
Basics of digital systems
Digital design flow
Field-Programmable Gate Arrays (FPGAs)
3a:Estimating chip area
3b:FPGA tutorial, 7 pages
4:FPGA vendors and major internal components
Tue, Jan 16   Verilog Introduction
Verilog Combinational logic
Verilog styles, delays, etc.
5:Verilog I: Intro and Combinational logicJAN 22
6:Verilog quick ref guide, S. Sutherland (skim quickly)
Th, Jan 18 Chapter 8 (Comb Blocks) Verilog wire, assign
Verilog Testing
Verilog Sensitivity Lists
 
Tue, Jan 23 Chapter 9 (Comb Examples) Quiz 1
Parameters, testing, sensitivity list wrapup
Combinational building blocks I: muxes
7:Verilog II: Intro and Combinational logic
Th, Jan 25   Verilog: Testing
Testbench design
8:Verilog III: TestingJAN 25, JAN 29 #134,147
Tue, Jan 30 Chapter 11 (Fixed/Float Pt)
Combinational building blocks II: case, casez
Combinational building blocks II: decoders
 
Th, Feb 1 Chapter 10 (Neg #s, Arith)
Quiz 2
Decoder implementations
Enabled blocks
Predecoding
Instantiating flip-flops I
 
Tue, Feb 6  
Instantiating flip-flops II
Reset-able and Enable-able flip-flops
9:FFs and registers
Th, Feb 8

Chapter 14 (Seq Logic)
Chapter 16 (Datapath Seq Logic)
Control I
10:Control
Tue, Feb 13   Midterm

Th, Feb 15 Chapter 15 (Timing)
Control II
Timing of digital systems
Clocks
 
Tue, Feb 20 Chapter 10 (Neg #s, Arith)
Chapter 17
Chapter 19
Arithmetic: ALUs
Comparators
ROMs
17:FFs rule#5
18:Clocks
Th, Feb 22 Chapter 25 Multi-rate clocks
Memory: major types
Memory: synthesized from verilog
19:Memories
20:Multi-rate clock examples
Tue, Feb 27 Chapter 23
Quiz 3
Pipelining
Edge detection
21:Edge detection
 
Th, March 1 Chapter 21
 
M9K memory blocks
Pipelining II
22:M9K memories
 
Tue, March 6 Chapter 22
 
System design
Static Timing Analysis
23:Nangate std cell library datasheet, Typical corner (see canvas Resources section)  
Th, March 8 Chapter 24
 
Static Timing Analysis II
Pipelined block diagrams
24:Static timing analysis
 
Tue, March 13  
 
Block interfaces, data flow
Block internal and external timing
 
Th, March 15 Chapter 20
Chapter 11 (Fixed/Float Pt)
 
Verification and test
Arithmetic: rounding and saturation
Arithmetic I: +, –; ripple, carry-select
Arithmetic II: ×, MAC, ÷
Optional: Fixed-point integers
Optional: Fixed-point fractional
Optional: Sign extension
Optional: Floating-point
 
Tue, March 20
8:00–10:00
  Final Exam

Assignments

Future details are tentative.

Week Prelab due and
work in Lab
Lab report due at
beginning of lab section
Hwk due
Friday 6:00 pm
in hwk box
Homework problems
(Problems in gray are tentative until approximately the Thurs 8 days
before the due date, depending on material covered in lecture)
January 8 – January 12 - - - -

January 15 – January 19 Lab 1
Modelsim/Quartus video tutorial
- - -

January 22 – January 26

Lab 2
Lab2.part2_testbench.v
Lab2.part3_template.v
Lab 1 -

January 29 – February 2

Lab 3JAN 31
Lab3.hdl.zip
testrom2.v
Lab3.expected.results.txt
Lab 2 -
February 5 – February 9

Lab 4
Lab 3 1
8.5, 8.12, 9.3, 9.9
February 12 – February 16
Lab 5
Demo Video
Lab 4 -
-



Changes made will generally be colored green, except basic information in tables.

Last update: February 11, 2018