TAs meet in 2110 Kemper unless noted otherwise.
12pm-4pm Lab A01
4pm-8pm Lab A04
5pm-9pm Lab A02
4pm-8pm Lab A03
|Jennifer Jean Pierre
8am-12pm Lab A06
1pm-5pm Lab A05
Prelabs. Except for Lab 1, prelabs are due at the beginning of the indicated lab section. They will be graded quickly on a scale from 0-5 points by your TA. The on-time deadline is 15 minutes after start of class. Unfortunately, points can not be given for the prelab portion after this time.
Lab circuit checkoffs are due at the beginning of the lab section
the following week immediately after prelab checkoffs (see Assignments
They are graded on the following scale (note there is no 4):
0 Little attempt made
1 Not fully built
2 All there, but not working
3 Just about correct
5 Totally correct
Lab reports are due at the same time as the lab circuit checkoffs. Due to the large amount of grading for TAs, and because of the fast pace of material in lab, credit for late lab reports is not possible.
Meets in 2110, Kemper Hall
Labs are normally open to you only during your assigned lab period. Your TA will normally close up the lab and ask students to leave at the end of the 4-hour lab period (esp. the night labs).
If you wish to work in the lab on Saturdays, it may be possible to open it. If you will definitely be there on a particular Saturday and need TA help, notify your TA and if there is sufficient interest, a TA will be there for part of the day.
Each lab period contains three main sub-periods:
Submit your Prelab to your TA as soon as you arrive and they will be checked-off and returned in the first ~10 minutes of the period.
You may go to another section and use the equipment only if there is space available. The students for that section have priority for the equipment and assistance from the TA. This is the priority for workstations in 2110 during lab times:
For several logistical reasons, only your section's TA can sign off your lab. I realize that is not the most convenient option for students, but it is necessary so TAs can focus on the students in their own section during labs. The only exception is that the TA present during a Saturday session may sign off only the circuit portions of labs for students from other sections.
Logging into computers in room 2110 requires that you have a standard ECE account name and password, which you should have if you are enrolled in the course. If you are having problems with your account, contact ECE IT support. To make sure the first lab goes smoothly, try to log in to a lab machine during open lab hours before your first lab. Files you save on your computer in 2110 are saved onto only the computer on which you work. So you will not see those files if you later work on a different computer. A nice solution is to make a copy of your files on a USB drive.
We will use the Quartus design tool to analyze and synthesize verilog designs. A free version has all the capabilities needed for 180B so that is what we will use. Downloading details are given in Lab 1. Other versions which require a license are available and may appear on workstations in Kemper 2110 however the operation of the functions are the same as with the free version.
Lab grades will be adjusted so the average grade for each section is the same—this removes unavoidable differences in grading from different TAs.
Normally TAs will not be able to debug students' circuits in detail so they are available for other students. If your TA agrees to assist you in debugging your circuit, show your TA your design materials and documentation first. Normally, TAs will focus on teaching debugging techniques rather than finding a particular bug in your design.
CAD tool locations on 2110 machines
Printing in 2110 Lab. There is a printer next to the front doors in room 2110. You may print lab-related documents to this printer using the printer "COE-ECE- LJ2110 on COE-IT- PCPRINT." After pressing File → Print, check that the highlighted printer listed in the box of devices at the top of the menu has this name; otherwise you may need to scroll left and right through the list of devices to find it.
No food or drinks are allowed in the lab. Unfortunately violations of this rule have gotten worse lately so the ECE staff is getting pretty strict on this rule. Equipment is connected to an alarm system so be careful to not move equipment which could set off the alarm.
The labs are mandatory components of this course.
A special thanks to Lance Halsted who developed or assisted in developing most of the labs.
Homeworks will normally be due late Friday afternoon in Room 2131 and will be returned in your lab section after grading. Unfortunately, late homeworks cannot be accepted except for verifiable medical excuses approved by the instructor.
Each major portion of each problem will be graded on a three-point scale: 0 (not a full effort), 1 (close but fundamental problem), and 2 (correct or with a very minor problem). For more challenging problems, points may be multiplied; e.g., [0,2,4 pts] or [0,3,6 pts].
The final exam is cumulative but with an emphasis on material since the midterm.
The course Collaboration Policy
|Date||Reading||Lecture||Notes, Handouts, and Reading|
|Tue, April 4||Chapter 1, 2||
Semiconductor fabrication technologies
|Th, April 6||
Skim Chapter 5
Basics of digital systems
Digital design flow
Field-Programmable Gate Arrays (FPGAs)
Verilog Combinational logic
2:FPGA tutorial, 7 pages
3:FPGA vendors and major internal componentsAPR 13 SLIDE 60
4:Verilog: Intro and Combinational logicAPR 11, APR 13 SLIDES 117-120
5:Verilog: TestingAPR 11, APR 13 SLIDES 143-147
6:Verilog quick ref guide, S. Sutherland (skim quickly)
|Tue, April 11||
Verilog Combinational logic II
Verilog styles, delays, etc.
Verilog Testing I
|Th, April 13||Chapter 8||
Verilog Testing II
Verilog Sensitivity Lists
Systems, chips, and boards
7:Estimating chip area
|Tue, April 18||Chapter 9||
Parameters, testing, sensitivity list wrapup
Combinational building blocks I
|Th, April 21||
Verilog Testing approaches
Combinational building blocks II: decoders
|Tue, April 25||
Combinational building blocks III: enabled blocks, predecoding, encoders,
|Th, April 27||Chapter 15||
Digital word formats
Arithmetic I: +, –
|Tue, May 2||Chapter 8||
Arithmetic II: ×, ÷, MAC, ALU, rounding
Timing of digital systems
Verilog Instantiating flip-flops
8:Verilog: FFs and registersAPR 11
|Th, May 4||Chapter 25||
Memory: single and multi-ported
|Tue, May 9||
|Th, May 11||
Memory: synthesized, block RAM, off-chip
|Tue, May 16|
|Th, May 18|
|Tue, May 23||
|Th, May 25|
|Tue, May 30|
|Th, June 1|
|Tue, June 6|
|Th, June 8|
|Fri, June 9
|Week||Prelab due and
work in Lab
|Lab report due at
beginning of lab section
Friday 6:00 pm
(Problems in gray are tentative until approximately the Thurs 8 days
before the due date, depending on material covered in lecture)
|April 3 – April 7||-||-||-||-
|April 10 – April 14||Lab 1APR 8, ADDED TESTBENCH DESCRIPTION||-||-||-
|April 17 – April 21||Lab 2APR 17, ADDED
Due Tue 6:00pm
|2.9, 2.10, 2.17, 2.18
|April 24 – April 28||
7.8, 7.14 (use 4-bit input instead), 7.15
8.1, 8.4, 8.9, 8.11, 8.15
|May 1 – May 5||Lab 4
8.19, 8.21 (output == 1 if input prime)
8.21B Draw detailed ROM circuit for 8.21
8.21C Write verilog for 8.21
9.1, 9.12, 9.13, 9.14. For 9.12-9.14, you will likely finish more quickly by using a straightforward algorithm rather than the book's
|May 8 – May 12||Lab 5||Lab 4||4
|May 15 – May 19||Lab 6||Lab 5||5
Last update: April 28, 2017