EEC 180B - Digital Systems II
Spring 2017

General Course Information

Lab Information

Course Policies

Course Topics, Slides, Notes, and Handouts

Future details are tentative.

Date Reading Lecture Notes, Handouts, and Reading
Tue, April 4 Chapter 1, 2 Course introduction
Semiconductor fabrication technologies
Lecture 01
1:Fabrication technologies        
Th, April 6 Skim Chapter 5
Chapter 7
Appendix A
Basics of digital systems
Digital design flow
Field-Programmable Gate Arrays (FPGAs)
Verilog Introduction
Verilog Combinational logic
2:FPGA tutorial, 7 pages
3:FPGA vendors and major internal componentsAPR 13 SLIDE 60
4:Verilog: Intro and Combinational logicAPR 11, APR 13, JUNE 1
5:Verilog: TestingAPR 11, APR 13 SLIDES 143-147
Tue, April 11   Verilog Combinational logic II
Verilog styles, delays, etc.
Verilog Testing I
6:Verilog quick ref guide, S. Sutherland (skim quickly)
Th, April 13 Chapter 8 Verilog Testing II
Verilog Sensitivity Lists
Systems, chips, and boards
FPGAs II
7:Estimating chip area
Tue, April 18 Chapter 9 Quiz 1
Parameters, testing, sensitivity list wrapup
Combinational building blocks I
 
Th, April 21   Verilog Testing approaches
Combinational building blocks II: decoders
 
Tue, April 25 Chapter 11
Combinational building blocks III: enabled blocks, predecoding, encoders
Comparators
 
Th, April 27 Chapter 10
Quiz 2
ROMs
Digital word format: Fixed-point integers
Arithmetic I: +, –
Sign extension
8:Adders & Subtractors
9:Sign extension
Tue, May 2  
Review of verilog modules
Digital word format: Fixed-point fractional
Arithmetic II: ×, MAC, ÷
10:Verilog: modules
11:Multipliers
Th, May 4 Chapter 15 Arithmetic III: ALUs
Instantiating flip-flops
Reset-able and Enable-able flip-flops
12:Rounding
13:Saturation
14:FFs and registersAPR 11, MAY 2
15:FF reset and enable
Modelsim/Quartus video tutorial
Tue, May 9   Midterm
Last name A-P: 180 MedSci C
Last name R-Z: 206 Olson
Th, May 11 Chapter 14
Chapter 16
Instantiating flip-flops overview
Control I
16:Control
 
Tue, May 16 Chapter 17
Chapter 19
Control II
Timing of digital systems
Clocks
17:FFs rule#5
18:Clocks
Th, May 18 Chapter 25 Multi-rate clocks
Memory: major types
Memory: synthesized from verilog
19:Memories
20:Multi-rate clock examples
Tue, May 23 Chapter 23
Quiz 3
Pipelining
Edge detection
21:Edge detection
 
Th, May 25 Chapter 21
 
M9K memory blocks
Pipelining II
22:M9K memories
 
Tue, May 30 Chapter 22
 
System design
Static Timing Analysis
23:Nangate std cell library datasheet, Typical corner (see smartsite Resources section)  
Th, June 1 Chapter 24
 
Static Timing Analysis II
Pipelined block diagrams
24:Static timing analysis
 
Tue, June 6  
 
Block interfaces, data flow
Block internal and external timing
 
Th, June 8 Chapter 20
 
Verification and test
Arithmetic IV: rounding and saturation
Optional: Digital word format: Floating-point
 
Fri, June 9
10:30-12:30
  Final Exam
Last name A–J: 206 Olson
Last name K–Z: 180 MedSci C

Assignments

Week Prelab due and
work in Lab
Lab report due at
beginning of lab section
Hwk due
Friday 6:00 pm
Homework problems
(Problems in gray are tentative until approximately the Thurs 8 days
before the due date, depending on material covered in lecture)
April 3 – April 7 - - - -

April 10 – April 14 Lab 1APR 8, TESTBENCH DESCRIPTION - - -

April 17 – April 21 Lab 2APR 17, GRADING SECTION
Lab2.part2_testbench.v
Lab2.part3_template.v
Lab 1 1
Due Tue 6:00pm
2.9, 2.10, 2.17, 2.18
April 24 – April 28 Lab 3
Lab3.zip
Lab 2 2
7.8, 7.14 (use 4-bit input instead), 7.15
8.1, 8.4, 8.9, 8.11, 8.15
May 1 – May 5 Lab 4MAY 4,10
Lab4.zip
Lab 3 3
8.19, 8.21 (output == 1 if input prime)
8.21B Draw detailed ROM circuit for 8.21
8.21C Write verilog for 8.21
9.1, 9.12, 9.13, 9.14. For 9.12-9.14, you will likely finish more quickly by using a straightforward algorithm rather than the book's
May 8 – May 12 Lab 5 - -
-

May 15 – May 19 Lab 6MAY 18
Lab6.zip Note switch signals must be mapped
Lab 4
Lab 5
-
-

May 22 – May 26 Lab 7MAY 26,29 Lab 6
4
19.1, 19.4, 19.9
25.1, 25.2a
Sat, May 27 Open Lab 11am–2pm
Open Lab 2–5pm
Mon, May 29 Memorial Day
Tue, May 30 Open Lab 11am–12pm
Open Lab 1–4pm
Open Lab 4–8pm
Wed, May 31 Open Lab 10am–11am
Open Lab 5–9pm
Th, June 1 Open Lab 10am–11am
Lab 7
(Sec. A03 due)
 
Fri, June 2 Open Lab 12pm–1pm
Lab 7
(Sec. A06,A05 due)
5 19.10
23.1–23.5, 23.8
21.1
Sat, June 3 Open Lab 10am–1pm
Open Lab 1–4pm
Mon, June 5 Open Lab 10am–11am
Open Lab 4pm–8pm
Lab 7
(Sec. A01 due)
 
Tue, June 6 Open Lab 8am–12pm
Lab 7
(Sec. A04 due)
 
Wed, June 7 Open Lab 10am–11am
Open Lab 1pm–5pm
Lab 7
(Sec. A02 due)
 
Th, June 8 No labs


Changes made will generally be colored green, except basic information in tables.

Last update: June 08, 2017