EEC 180B - Digital Systems II
Spring 2017

General Course Information

Lab Information

Course Policies

Course Topics, Slides, Notes, and Handouts

Future details are tentative.

Date Reading Lecture Notes, Handouts, and Reading
Tue, April 4 Chapter 1, 2 Course introduction
Semiconductor fabrication technologies
Lecture 01
1:Fabrication technologies        
Th, April 6 Skim Chapter 5
Chapter 7
Appendix A
Basics of digital systems
Digital design flow
Field-Programmable Gate Arrays (FPGAs)
Verilog Introduction
Verilog Combinational logic
2:FPGA tutorial, 7 pages
3:FPGA vendors and major internal componentsAPR 13 SLIDE 60
4:Verilog: Intro and Combinational logicAPR 11, APR 13 SLIDES 117-120
5:Verilog: TestingAPR 11, APR 13 SLIDES 143-147
6:Verilog quick ref guide, S. Sutherland (skim quickly)
Tue, April 11   Verilog Combinational logic II
Verilog styles, delays, etc.
Verilog Testing I
 
Th, April 13 Chapter 8 Verilog Testing II
Verilog Sensitivity Lists
Systems, chips, and boards
FPGAs II
7:Estimating chip area
Tue, April 18 Chapter 9 Quiz 1
Parameters, testing, sensitivity list wrapup
Combinational building blocks I
 
Th, April 21   Verilog Testing approaches
Combinational building blocks II: decoders
 
Tue, April 25 Chapter 10
Chapter 11  
Combinational building blocks III: enabled blocks, predecoding, encoders, comparators
 
Th, April 27 Chapter 15 Quiz 2
ROMs
Digital word formats
Arithmetic I: +, –
 
Tue, May 2 Chapter 8 Arithmetic II: ×, ÷, MAC, ALU, rounding
Timing of digital systems
Verilog Instantiating flip-flops
8:Verilog: FFs and registersAPR 11
Th, May 4 Chapter 25 Memory: single and multi-ported

 
Tue, May 9   Midterm

Th, May 11   Memory: synthesized, block RAM, off-chip
 
 
Tue, May 16      
Th, May 18      
Tue, May 23   Quiz 3
 
 
Th, May 25      
Tue, May 30      
Th, June 1      
Tue, June 6      
Th, June 8      
Fri, June 9
10:30-12:30
  Final Exam

Assignments

Future details are tentative.

Week Prelab due and
work in Lab
Lab report due at
beginning of lab section
Hwk due
Friday 6:00 pm
Homework problems
(Problems in gray are tentative until approximately the Thurs 8 days
before the due date, depending on material covered in lecture)
April 3 – April 7 - - - -

April 10 – April 14 Lab 1APR 8,  ADDED TESTBENCH DESCRIPTION - - -

April 17 – April 21 Lab 2APR 17,  ADDED GRADING SECTION
Lab2.part2_testbench.v
Lab2.part3_template.v
Lab 1 1
Due Tue 6:00pm
2.9, 2.10, 2.17, 2.18
April 24 – April 28 Lab 3
Lab3.zip
Lab 2 2
7.8, 7.14 (use 4-bit input instead), 7.15
8.1, 8.4, 8.9, 8.11, 8.15
May 1 – May 5 Lab 4
Lab4.zip
Lab 3 3
8.19, 8.21 (output == 1 if input prime)
8.21B Draw detailed ROM circuit for 8.21
8.21C Write verilog for 8.21
9.1, 9.12, 9.13, 9.14. For 9.12-9.14, you will likely finish more quickly by using a straightforward algorithm rather than the book's
May 8 – May 12 Lab 5 Lab 4 4


May 15 – May 19 Lab 6 Lab 5 5




Changes made will generally be colored green, except basic information in tables.

Last update: April 28, 2017