Digital signal processors, building blocks, and algorithms. Design and implementation of processor algorithms, architectures, control, functional units, and circuit topologies for increased performance and reduced circuit size and power dissipation.
Goals: Through this course, students will develop the necessary skills to design simple synthesizable processors suitable for numerically intensive processing with an emphasis on small chip area and highperformance. Secondly, students will learn to design processors for simple digital signal processing tasks through the simultaneous design of DSP algorithms, processor architectures, and hardware design.
Quizzes cover material through the end of the previous lecture with an emphasis on material since the last quiz.
The final exam is a mandatory component of this course. It is designed to test a working knowledge and understanding of concepts, not just mechanical procedures. You may bring one page of doublesided handwritten (no photocopying) notes to the final exam.
Read by  Paper  Comments 
Th, Jan 12  Programmable DSP Architectures: Part I, Edward A. Lee, ASSP Magazine, October 1988.  Easy to read article on the most notable features of programmable DSP processors. These firstgeneration DSP processors were more clearly distinguished from generalpurpose processors than they are today. Note the publication date of 1988many of the technical specifications are impressive only when considered in the context of the technology available at that time. 
Reference  Programmable DSP Architectures: Part II, Edward A. Lee, ASSP Magazine, January 1989.  Easy to read article presenting an overview of issues of programming pipelined DSP processors with complex organizations. 
Tue, Jan 17  Notes on ECE Machines and Tool Setup

Notes on ECE linux machines and your CAD tool environment setup 
Tue, Jan 17  Notes on Running Verilog 
Notes on running ncverilog here at UC Davis 
Tue, Jan 17  Example code 
Verilog code that may be helpful 
Tue, Jan 17  Quick Reference For Verilog,
Rajeev Madhavan
[2up] 
A very helpful and handy verilog reference 
Tue, Jan 17 Skim. 
Verilog According To Tom, Tom Chanak  Old but helpful intro to verilog. Please also read our accompanying notes. Skim. 
Tue, Jan 17 Skim. 
An Online Verilog Reference, S. Sutherland  Convenient and very nicely presented. Note that it covers aspects of verilog that shouldn't be used for sythesizable code, such as signal strengths and primitives. 
Reference  A Signed Binary Multiplication Technique, A. D. Booth, Quarterly Journal of Mechanics and Applied Mathematics, June 1951.  Classic paper introduces the Booth Algorithm. 
Reference  Highspeed Arithmetic in Binary Computers, O. L. MacSorley, Proceedings of the IRE, January 1961.  Classic paper introduces the Modified Booth's Algorithm which is commonly used in hardware implementations. 
Tue, Jan 31  SPIM: A Pipelined 64 x 64bit Iterative Multiplier, M. Santoro and M. Horowitz, IEEE Journal of SolidState Circuits, April 1989.  Classic paper is apparently the first to describe the 4:2 adder. It certainly contributed to the popular use of the 4:2 and its use in adding multiplier partial products. 
Tue, Feb 7  Notes on Running Design Compiler 
Notes and starter files for Synopsys' Design Compiler, and details on our standard cell library 
Tue, Feb 14  Notes for running matlab Simple matlab functions useful for 281FEB 23 Illustrative matlab examplesFEB 23 
Notes for running matlab here at UC Davis, and some useful matlab functions and examples 
Th, Feb 23 Skim. 
An Algorithm for the Machine Calculation of Complex Fourier Series, James W. Cooley and John W. Tukey, Mathematics of Computation, April 1965.  The paper that popularized FFTs. 
Th, Feb 23 Skim. 
Historical Notes on the Fast Fourier Transform, James W. Cooley, Peter A. W. Lewis, and Peter D. Welch; Proceedings of the IEEE, October 1967.  Some notes on FFT history 2 years after the seminal paper. 
Th, Mar 8  Trends in Multicore DSP Platforms, Karam, AlKamal, Gatherer, Frantz, Anderson, Evans, IEEE Signal Processing Magazine, November 2009.  A paper with a thorough and detailed survey of modern multicore DSP processors 
Reference  A 28nm 0.6V LowPower DSP for Mobile Applications, G. Gammie et al.  A paper presented at ISSCC 2011. 
Reference  A 275mW Heterogeneous Multimedia Processor for ICStacking on SiInterposer, H.E. Kim et al.  A paper presented at ISSCC 2011. 
Number  Due Date  % Hwk/proj grade  Material covered 
1 
Friday, Jan 27, 4:30pm  15%  Binary arithmetic and conversion, verilog, and manyinput adders 
2 
Friday, Feb 17, 4:30pm  20%  Synthesis, multipliers, state machine 
3 
Wednesday, March 8, 4:30pm  30%  FIR filters, Design block 
4 
Friday, March 24, 1:00pm  35%  Cognitive radio spectrum analyzer 
If an assignment is reviewed in class, no credit is possible for late work. If an assignment was not reviewed in class, there will be a 1/3 reduction of remaining credit per day (i.e., 100% → 67% → 44% → 30% ...).
To request a regrade, submit: 1) a short description of the suspected grading error, 2) the following statement on your regrade request with your signature immediately below it: "I certify that I have not altered this work in any way after it was returned to me. I understand that such altering would constitute a violation of the Code of Academic Conduct."
Date  Lecture  Handouts  Topics 
Tue, January 10  1 
Lecture 01 1:Fabrication Technologies 2:Quantization Noise 
Course introduction, DSP overview,
overview of "context" implementation technologies 
Th, January 12  2  3:Sign Extension  MAC; FIR, convolution, dot products Number representations: integer 
Tue, January 17  3  4:Floating Point 
Number representations: fractional, unsigned, signed;
Sign extension;
Floating point,
Block floating point,
Redundant number representations (carrysave),
3:2 and 4:2 carrysave adders,

Th, January 19  4  5:Verilog I 
Fast carrysave addition,
Verilog I,

Tue, January 24  5 
6:Verilog testing 7:Pipelined Block Diagrams 8:Adders 
Hardware verilog vs. testing verilog, Adders: carrypropagate vs. carrysave Subtraction, ripple, carryselect adders Carrylookahead adders 
Th, January 26  6 
9:Efficient Multiple Input Addition 10:Multipliers 
Multipleinput signed addition, Multipliers, Booth encoding, 
Tue, January 31  7 
Quiz 1 (25%) 11:Example Multiplier 12:Synthesis 13:Verilog II FEB 9, SLIDE 205 
Multipliers II, Synthesis, Verilog II, 
Th, February 2  8 
14:Verilog Control 15:Drive Through Processing 
Drive through processing, Control circuits, state machine design 
Tue, February 7 (ISSCC)  9 
16:Squaring 17:Fixed Input MultiplicationFEB 9, SLIDE 241 18:Multiplier Scaling 
Quiz 1 review, Squaring, Fixedinput multiplies, Multiplication scaling 
Th, February 9  10 
19:Complex ArithmeticFEB 9, SLIDES 262263 
Complex addition, mult, rotation, format conversion; 
Tue, February 14  11 
Quiz 2 (35%) 20:Complex Signal Magnitude Estimation 21:SaturationFEB 23, SLIDES 277284; FEB 28, SLIDES 279280 22:RoundingFEB 16, SLIDES 296299 
Complex magnitude estimation, Saturation and Compression, Rounding, 
Th, February 16  12 
23:Fourier Pairs 24:dB 
Fourier Transform, Filters, 
Tue, February 21  13 
25:Filter Coefficient Design 26:Estimating Spectral Magnitude 27:FIR Scaling 
Filter design 
Th, February 23 
14 
28:DFT & FFT Background 29:FFT Algorithms 
Discrete Fourier transform (DFT), fast Fourier transform (FFT) 
Tue, February 28 
15 
Quiz 3 (40%) 30:The RRI FFT 31:FFT Spiffee Example 32:FFT Chips 33:Memories 
FFT processor architectures, FFT processor example, Memories: structure, types (6T SRAM, multiport SRAM, ROM, DRAM), uses in standardcell ASIC designs 
Th, March 2 
16 
34:Multirate signal processing 35:downsamp_movie.m 
Multirate processing, Upsampling, decimation, 
Tue, March 7  17 
36:Clocks 37:Nyquist Filters 
Clock design, Nyquist filters, Nyquist filters with upsampling, 
Th, March 9 
18 
38:DC Offset 39:Automatic gain control 40:Multiple Access 41:CDMA 42:DSSS Spreadsheet 
DC offset, Automatic gain control, Multiple access, Spread spectrum, CDMA, DSSS, 
Tue, March 14 
19 
43:Viterbi Decoding 
Viterbi decoders 
Th, March 16 
20 

Convolution using DFT/FFTs 
Wed, March 22 1:003:00pm 
Final Exam 
I. Digital signal processing overview A. DSP workloads B. Example applications C. Programmable processors II. Processor building blocks A. Verilog hardware description language B. Binary number representations C. Carrypropagate adders D. Carrysave adders E. Multipliers F. Fixedinput multipliers G. Complex arithmetic hardware H. Memories III. DSP algorithms and systems A. FIR filtering B. Processor control and datapath integration C. Multirate signal processing D. Example systems: FFT, Viterbi, DSSS, CDMA,. IV. Design optimization A. Verilog synthesis to a gate netlist B. Delay estimation and reduction C. Area estimation and reduction D. Power estimation and reduction