Prerequisites: EEC 150B, EEC 170, and EEC 180B; or consent of instructor
Catalog description
Digital signal processors, building blocks, and algorithms. Design and implementation of processor algorithms, architectures, control, functional units, and circuit topologies for increased performance and reduced circuit size and power dissipation.
Goals: Through this course, students will develop the necessary skills to design simple synthesizable processors suitable for numerically intensive processing with an emphasis on small chip area and high-performance. Secondly, students will learn to design processors for simple digital signal processing tasks through the simultaneous design of DSP algorithms, processor architectures, and hardware design.
Quizzes cover material through the end of the previous lecture with an emphasis on material since the last quiz.
The final exam is a mandatory component of this course. It is designed to test a working knowledge and understanding of concepts, not just mechanical procedures. You may bring one page of double-sided hand-written (no photocopying) notes to the final exam.
Read by | Paper | Comments |
Th, Jan 11 | Programmable DSP Architectures: Part I, Edward A. Lee, ASSP Magazine, October 1988. | Easy to read article on the most notable features of programmable DSP processors. These first-generation DSP processors were more clearly distinguished from general-purpose processors than they are today. Note the publication date of 1988--many of the technical specifications are impressive only when considered in the context of the technology available at that time. |
Reference | Programmable DSP Architectures: Part II, Edward A. Lee, ASSP Magazine, January 1989. | Easy to read article presenting an overview of issues of programming pipelined DSP processors with complex organizations. |
Tue, Jan 16 |
Notes on ECE Machines and Tool Setup
Notes on a few useful linux commands |
Notes on ECE linux machines and your CAD tool environment setup
Notes on a few useful linux commands |
Tue, Jan 16 |
verilog: notes on running it verilog: common pitfalls with suggestions verilog: example code |
Notes on running ncverilog here at UC Davis |
Tue, Jan 16 |
Quick Reference For Verilog,
R. Madhavan
[2up]
Verilog Quick Reference Guide, S. Sutherland, skim it |
A very helpful and handy verilog reference.
Convenient and very nicely presented. Note that it covers aspects of verilog that shouldn't be used for sythesizable code such as signal strengths and primitives. [original] |
Reference | A Signed Binary Multiplication Technique, A. D. Booth, Quarterly Journal of Mechanics and Applied Mathematics, June 1951. | Classic paper introduces the Booth Algorithm. |
Reference | High-speed Arithmetic in Binary Computers, O. L. MacSorley, Proceedings of the IRE, January 1961. | Classic paper introduces the Modified Booth's Algorithm which is commonly used in hardware implementations. |
Tue, Jan 30 | SPIM: A Pipelined 64 x 64-bit Iterative Multiplier, M. Santoro and M. Horowitz, IEEE Journal of Solid-State Circuits, April 1989. | Classic paper is apparently the first to describe the 4:2 adder. It certainly contributed to the popular use of the 4:2 and its use in adding multiplier partial products. |
Tue, Feb 6 | Notes on Running Design Compiler |
Notes and starter files for Synopsys' Design Compiler, and details on our standard cell library |
Tue, Feb 13 |
matlab: notes for running matlab: simple functions useful for 281 matlab: illustrative examples |
Notes for running matlab here at UC Davis, and some functions and examples |
Th, Feb 22 Skim. |
An Algorithm for the Machine Calculation of Complex Fourier Series, James W. Cooley and John W. Tukey, Mathematics of Computation, April 1965. | The paper that popularized FFTs. |
Th, Feb 22 Skim. |
Historical Notes on the Fast Fourier Transform, James W. Cooley, Peter A. W. Lewis, and Peter D. Welch; Proceedings of the IEEE, October 1967. | Some notes on FFT history 2 years after the seminal Cooley & Tukey paper. |
Th, Mar 7 | Trends in Multicore DSP Platforms, Karam, AlKamal, Gatherer, Frantz, Anderson, Evans, IEEE Signal Processing Magazine, November 2009. | A paper with a thorough and detailed survey of modern multicore DSP processors |
Number | Due Date | % Hwk/proj grade | Material covered |
1 |
Thursday, Feb 1, 9:00am | 25% | Binary arithmetic and conversion, verilog, and many-input adders |
2 |
Friday, Feb 23, 4:00pm | 20% | Synthesis, multipliers, state machine |
3 |
Wednesday, March 14, 4:00pm | 35% | Partial product scaling, Complex exponential generator |
4 |
Wednesday, March 21, 4:00pm | 20% |
All work for a particular hwk/project must be submitted at one time.
If an assignment is reviewed in class, no credit is possible for late work. If an assignment was not reviewed in class, there will be a 1/3 reduction of remaining credit per day (i.e., 100% → 67% → 44% → 30% ...).
Normally late work can not be accepted after its deadline however if a serious issue such as an illness prevents you from completing work on time, obtain a verifiable written excuse, bring it to the instructor, and something will be worked out.
To request a regrade, submit: 1) a short description of the suspected grading error, 2) the following statement on your regrade request with your signature immediately below it: "I certify that I have not altered this work in any way after it was returned to me. I understand that such altering would constitute a violation of the Code of Academic Conduct."
Date | Lecture | Handouts | Topics |
Tue, January 9 | 1 |
1:Lecture 01 2:Fabrication Technologies |
Course introduction, DSP overview, overview of "context" implementation technologies |
Th, January 11 | 2 | Multiply-accumulate FIR, convolution, dot products | |
Tue, January 16 | 3 |
3:Quantization Noise
and Word Size 4:Sign Extension |
Quantization noise and Word size Number representations: integer, unsigned, signed Sign extension for 2's complement Number representations: fractional |
Th, January 18 | 4 |
5:Floating Point |
Number representations: Floating point, Block floating point Number representations: Redundant (carry-save) 3:2 and 4:2 carry-save adders Fast carry-save addition |
Tue, January 23 | 5 |
6:Verilog IJAN 23 |
Verilog I: basics Hardware verilog vs. testing verilog |
Th, January 25 | 6 |
Quiz 1 7:Verilog II: testingJAN 25, JAN 29 #134 |
Verilog II: testing Testbench design |
Tue, January 30 | 7 |
8:Pipelined Block Diagrams 9:Adders 10:Efficient Multiple Input Addition |
Pipelined block diagrams Adders: carry-propagate vs. carry-save Carry-lookahead adders Subtraction, ripple, carry-select adders Multiple-input signed addition |
Th, February 1 | 8 |
11:MultipliersFEB 2 #192-197 |
Multipliers Booth encoding |
Tue, February 6 | 9 |
12:Example Multiplier 13:Verilog FFs and registers |
Multipliers II Verilog FFs and registers |
Th, February 8 | 10 |
14:Synthesis |
Synthesis |
Tue, February 13 (ISSCC) | 11 |
Quiz+ 2 18:Squaring 19:Fixed Input Multiplication |
Squaring Fixed-input multiplies I |
Th, February 15 | 12 |
15:Verilog ControlFEB 21 #264-266, 270 |
Fixed-input multiplies II Control circuits, state machine design |
Tue, February 20 | 13 |
16:Drive Through Processing 17:Gen Complex FunctionsFEB 26 #280 |
Drive through processing Generating complex functions |
Th, February 22 |
14 |
20:Multiplier Scaling 21:Complex Arithmetic |
Multiplication scaling Complex addition, multiplication, rotation, format conversion |
Tue, February 27 |
15 |
22:Complex Signal Magnitude Estimation 23:SaturationMAR 8 |
Complex magnitude estimation Saturation and Compression |
Th, March 1 |
16 |
Quiz 3 24:RoundingMAR 4, MAR 5 25:Signals in Time and FrequencyMAR 6 |
Rounding Signals in time and frequency |
Tue, March 6 | 17 |
26:dB 27:Digital Filter Coefficient Design 28:Estimating Spectral Magnitude |
dB Digital filter hardware Digital filter coefficient design Estimating spectral magnitude of signals |
Th, March 8 |
18 |
29:FIR Scaling 30:MemoriesMAR 12 31:Multi-rate signal processing 32:downsamp_movie.m |
FIR scaling Memories: structure, types (6T SRAM, multi-port SRAM, ROM, DRAM), uses in standard-cell ASIC designs Multi-rate processing Upsampling, decimation |
Tue, March 13 |
19 |
33:ClocksMAR 13 34:Variable-freq clocksMAR 13 35:Nyquist FiltersMAR 13 36:DFT & FFT Background 37:FFT AlgorithmsMAR 15 |
Clock design Nyquist filters Nyquist filters with upsampling Discrete Fourier transform (DFT) fast Fourier transform (FFT) FFT processor architectures |
Th, March 15 |
20 |
38:The RRI FFT 39:FFT Spiffee Example 40:FFT Chips 41:Viterbi Decoding 42:Multiple Access 43:CDMA 44:DSSS Spreadsheet |
FFT processor example Linear convolution using DFT/FFTs Viterbi decoders Multiple access Spread spectrum, CDMA, DSSS |
Th, March 22 3:30–5:30pm |
Final Exam |
I. Digital signal processing overview A. DSP workloads B. Example applications C. Programmable processors II. Processor building blocks A. Verilog hardware description language B. Binary number representations C. Carry-propagate adders D. Carry-save adders E. Multipliers F. Fixed-input multipliers G. Complex arithmetic hardware H. Memories III. DSP algorithms and systems A. FIR filtering B. Processor control and datapath integration C. Multi-rate signal processing D. Example systems: FFT, Viterbi, DSSS, CDMA,. IV. Design optimization A. Verilog synthesis to a gate netlist B. Delay estimation and reduction C. Area estimation and reduction D. Power estimation and reduction