Digital signal processors, building blocks, and algorithms. Design and implementation of processor algorithms, architectures, control, functional units, and circuit topologies for increased performance and reduced circuit size and power dissipation.
Goals: Through this course, students will develop the necessary skills to design simple synthesizable processors suitable for numerically intensive processing with an emphasis on small chip area and high-performance. Secondly, students will learn to design processors for simple digital signal processing tasks through the simultaneous design of DSP algorithms, processor architectures, and hardware design.
Quizzes cover material through the end of the previous lecture with an emphasis on material since the last quiz.
The final exam is a mandatory component of this course. It is designed to test a working knowledge and understanding of concepts, not just mechanical procedures. You may bring one page of double-sided hand-written (no photocopying) notes to the final exam.
Read by | Paper | Comments |
Th, Jan 8 | Programmable DSP Architectures: Part I, Edward A. Lee, ASSP Magazine, October 1988. | Easy to read article on the most notable features of programmable DSP processors. These first-generation DSP processors were more clearly distinguished from general-purpose processors than they are today. Note the publication date of 1988--many of the technical specifications are impressive only when considered in the context of the technology available at that time. |
Optional reference | Programmable DSP Architectures: Part II, Edward A. Lee, ASSP Magazine, January 1989. | Easy to read article presenting an overview of issues of programming pipelined DSP processors with complex organizations. |
Tue, Jan 13 | Notes on ECE Machines and Tool Setup | Notes on ECE linux machines and your CAD tool environment setup |
Tue, Jan 13 | Notes on Running Verilog | Notes on running ncverilog here at UC Davis |
Tue, Jan 13 | Example code | Verilog code that may be helpful |
Tue, Jan 13 | Quick Reference For Verilog, Rajeev Madhavan [2up] | A very helpful and handy verilog reference |
Tue, Jan 13 Skim. |
Verilog According To Tom, Tom Chanak | Old but helpful intro to verilog. Please also read our accompanying notes. Skim. |
Tue, Jan 13 Skim. |
An On-line Verilog Reference, S. Sutherland | Convenient and very nicely presented. Note that it covers aspects of verilog that shouldn't be used for sythesizable code, such as signal strengths and primitives. |
Optional reference | A Signed Binary Multiplication Technique, A. D. Booth, Quarterly Journal of Mechanics and Applied Mathematics, June 1951. | Classic paper introduces the Booth Algorithm. |
Optional reference | High-speed Arithmetic in Binary Computers, O. L. MacSorley, Proceedings of the IRE, January 1961. | Classic paper introduces the Modified Booth's Algorithm which is commonly used in hardware implementations. |
Th, Jan 29 | SPIM: A Pipelined 64 x 64-bit Iterative Multiplier, M. Santoro and M. Horowitz, IEEE Journal of Solid-State Circuits, April 1989. | Classic paper adds to the popularity of the 4:2 adder and its use in adding multiplier partial products. |
Th, Feb 12 | Notes on Running Matlab | Notes on running matlab here at UC Davis, and some useful matlab functions |
Th, Feb 12 | Notes on Running Design Compiler | Notes and starter files for Synopsys' Design Compiler, and details on our standard cell library |
Th, Feb 19 Skim. |
An Algorithm for the Machine Calculation of Complex Fourier Series, James W. Cooley and John W. Tukey, Mathematics of Computation, April 1965. | The paper that popularized FFTs. |
Th, Feb 19 Skim. |
Historical Notes on the Fast Fourier Transform, James W. Cooley, Peter A. W. Lewis, and Peter D. Welch; Proceedings of the IEEE, October 1967. | Some notes on FFT history 2 years after the seminal paper. |
Th, Mar 4 | Trends in Multicore DSP Platforms, Karam, AlKamal, Gatherer, Frantz, Anderson, Evans, IEEE Signal Processing Magazine, November 2009. | A paper with a thorough and detailed survey of modern multicore DSP processors |
Optional reference | A 28nm 0.6V Low-Power DSP for Mobile Applications, G. Gammie et al. | A paper presented at ISSCC 2011. |
Optional reference | A 275mW Heterogeneous Multimedia Processor for IC-Stacking on Si-Interposer, H.-E. Kim et al. | A paper presented at ISSCC 2011. |
Number | Due Date | % Hwk/proj grade | Material covered |
1 | Mon, Jan. 26 | 15% | Binary arithmetic and conversion, verilog, and many-input adders |
2 | Th, Feb. 12 | 20% | Synthesis and multipliers |
3 | Th, Mar. 5 | 30% | FIR filters |
4 | Tue, Mar. 17 | 35% | TBD |
Date | Lecture | Handouts | Topics |
Tue, January 6 | 1 | Lecture 01 | Course introduction, DSP overview, overview of "context" implementation technologies |
Th, January 8 | 2 |
1:QuantizationNoise |
MAC; FIR, convolution, dot products Number representations: integer |
Tue, January 13 | 3 | 3:SignExtension | Number representations: fractional, unsigned, signed; Sign extension; Floating point, |
Th, January 15 | 4 | 4:FloatingPt, 5:Verilog I | block floating point, redundant number representations (carry-save), 3:2 and 4:2 carry-save adders; Verilog I, |
Tue, January 20 | 5 | 6:Verilog testing | Verilog I, |
Th, January 22 | 6 |
Quiz 1 (25%) 7:EfficMultInputAddition |
Hardware verilog vs. testing verilog,
Adders: carry-propagate vs. carry-save Subtraction, ripple, carry-select adders Carry-lookahead adders |
Tue, January 27 | 7 | 8:BoothEnc, 9:ExampMult 10:Synthesis, |
Multiple-input signed addition Multipliers, Booth encoding, Synthesis, |
Th, January 29 | 8 | 11:Verilog II, 12:VerilogControl |
Verilog II,
Control circuits, state machine design, enableable registers |
Tue, February 3 | 9 | 13:DriveThroughProc, |
Drive through processing, Squaring |
Th, February 5 | 10 |
Quiz 2 (25%) 14:Squaring, 15:FixedInputMults, 16:MultScaling, 17:ComplexArith, |
Fixed-input multiplies and scaling; complex arithmetic |
Tue, February 10 | 12 | 18:ComplexSigMagEst, 19:Saturation, 20:Rounding, 21:FourierPairs, |
Complex rotations, conversions, and amplitude estimation,
Saturation, rounding, Fourier Transform, |
Th, February 12 | 13 | 22:dB, 23:FiltCoeffDesign, 24:SignalMags, | Filters, filter design |
Tue, February 17 | 14 | 25:FilterResponse, 26:FIRScaling, | Filter design II |
Th, February 19 |
15 | 27:DFT&FFTbackground, 28:FFTDiagramsAlgs, | Discrete Fourier transform (DFT), fast Fourier transform (FFT) |
Tue, February 24 (ISSCC) |
16 |
Quiz 3 (50%) 29:FFT.RRI, |
FFT processors |
Th, February 26 |
17 | 30:FFTspiffee, 31:FFTchips, |
FFT processor example, |
Tue, March 3 | 18 | 32:Memories, 33:Multi-rate, 34:Upsampling, 35:Decimation | Memories: structure, types (6T SRAM, multi-port SRAM, ROM, DRAM) Multi-rate processing, Upsampling, decimation, |
Th, March 5 |
19 | downsamp_movie.m, 36:MultipleAccess, 37:CDMA, 38:DSSSspreadsheet, 39:NyquistFilters |
Multiple access,
Spread spectrum, CDMA, DSSS, Nyquist filters, Nyquist filters with upsampling, |
Tue, March 10 |
20 | 40:DCoffset, 41:Automatic gain control |
DC offset, Automatic gain control, |
Th, March 12 |
20 | 42:Viterbi |
Viterbi decoders Convolution using DFT/FFTs; Area, speed, power tradeoffs |
Wed, March 18 3:30-5:30pm |
Final Exam |
I. Digital signal processing overview A. DSP workloads B. Example applications C. Programmable processors II. Processor building blocks A. Verilog hardware description language B. Binary number representations C. Carry-propagate adders D. Carry-save adders E. Multipliers F. Fixed-input multipliers G. Complex arithmetic hardware H. Memories III. DSP algorithms and systems A. FIR filtering B. Processor control and datapath integration C. Multi-rate signal processing D. Example systems: FFT, Viterbi, DSSS, CDMA,. IV. Design optimization A. Verilog synthesis to a gate netlist B. Delay estimation and reduction C. Area estimation and reduction D. Power estimation and reduction
Submit to the instructor: 1) a short description of the suspected grading error, 2) the following statement on your regrade request with your signature immediately below it: "I certify that I have not altered this work in any way after it was returned to me. I understand that such altering would constitute a violation of the Code of Academic Conduct."