EEC 281 - Homework/Project #2

Winter 2015

Work individually, but I strongly recommend working with someone in the class nearby so you can help each other when you get stuck, with consideration to the course collaboration policy. Please send me email if something isn't clear and I will update the assignment. Changes are logged at the bottom of this page.

Notes:


Total: 230 points

For this homework/project, you may use the
  always @(*)
verilog construct but first make sure Design Compiler is compatible with it.

All adders and multipliers in Problems 2–6 should have only one register at the inputs and one at the outputs and no more (so they can be compared).

  1. [25 pts] The purpose of this problem is to familiarize you with the synthesis process and to give you a rough feeling for the size of a few simple circuits in our standard cell library's technology. Copy the files from the DC tutorial (see link on main EEC281 page) to get started. Synthesize the following blocks and report their total cell area. Do not include registers (flip-flops) in these blocks. Also, do not declare any wires or registers as "signed", but assume words are all 2's complement signed unless stated otherwise. No need to simulate or turn in any files other than the source verilog, but your verilog must compile correctly (run "make check").

    For this problem, do not worry if designs do not meet timing (negative slack time). Report totals in a single table so it can be used as a note sheet in the future.

    For this problem, do not submit the 5 synthesis reports listed above.

    Blocks

    a) [2 pts] bitwise OR of two 10-bit numbers (10-bit output)

    b) [2 pts] 3:2 adder using verilog "&" "|", "^", "~".
    Draw your circuit and the circuit output by DC.

    c) [2 pts] 3:2 adder using verilog "+".

    d) [3 pts] 10-bit adder (11-bit output). Use "+" in verilog.

    e) [5 pts] an adder which adds 33 7-bit numbers using verilog "+" (i.e., something like, assign out = in0 + in1 + in2 + ...) and produces a 7-bit sum.

    f) [5 pts] your 33-input adder from hwk/proj 1, Problem 6. If your adder is not functional, improve it so it is at least synthesizable, synthesize it anyway, and write a note on your submission that it is not functional.

    g) [3 pts] 8-bit x 8-bit unsigned multiplier (16-bit output). Use "*" in verilog.

    h) [3 pts] 16-bit x 16-bit unsigned multiplier (32-bit output). Use "*" in verilog.


  2. [20 pts] Build a ripple-carry adder with 16-bit inputs and 16-bit output using full adders from part 1(c). Register all inputs and outputs (to make synthesis timing accurate).

    a) [10 pts] Write design in verilog, test with at least 15 test cases. Verify using method ***(3).

    b) [10 pts] Synthesize the design with a high clock frequency to find the maximum clock rate. State the maximum clock rate and corresponding area. Submit *.area and *.tim (longest path only) reports only.


  3. [25+10 pts] Repeat Problem 2 with a carry-select adder composed of two 8-bit sections.


  4. [25+10+10 pts] Repeat Problem 2 with a carry-select adder composed of three sections whose widths are chosen to minimize delay.

    c) [10 pts] Justify the partitioning you chose.


  5. [45 pts] Build an 8-bit x 8-bit non-Booth multiplier where both inputs are in unsigned format. Use carry-save adders to add partial products and your carry-select adder from Problem 4 (without its registers) for the final CPA. Register all inputs and outputs of the entire multiplier block (to make synthesis timing accurate).

    a) [10 pts] Draw all dot diagrams including all adders

    b) [25 pts] Write design in verilog, test with at least 15 test cases in addition to the ones listed below. Verify using method ***(3).

                  0     x           0
                  0     x           1
                  1     x           0
                  1     x           1
                  1     x           2
                  2     x           1
                  1     x         128
                128     x           1
                  1     x     max pos
            max pos     x           1
            max pos     x     max pos
            
    c) [10 pts] Synthesize the design with a high clock frequency to find the maximum clock rate. State the maximum clock rate and corresponding area. Submit *.area and *.tim (longest path only) reports only.


  6. [10+35+10 pts] Repeat Problem 5 with a Booth-2 multiplier with 2's complement inputs.


  7. [5 pts] Write a table with 1) max clock frequency and 2) area for problems 2–6.



Updates:

2015/02/01  Posted